SCAS970 February   2024 SN74AHC164

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6.   6
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     14
    8. 5.7 Switching Characteristics
    9. 5.8 Noise Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
      1. 8.3.1 Power Considerations
      2. 8.3.2 Input Considerations
      3. 8.3.3 Output Considerations
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curve
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|14
  • BQA|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 85°C -40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
tSU Setup time CLR high 3.3V ± 0.3V 2.5 2.5 2.5 ns
tSU Setup time Data before CLK↑ 3.3V ± 0.3V 5 6 6 ns
tH Hold time Data after CLK↑ 3.3V ± 0.3V 0 0 0 ns
tW Pulse duration CLK high or low 3.3V ± 0.3V 5 5 5 ns
tW Pulse duration CLR low 3.3V ± 0.3V 5 5 5 ns
tSU Setup time CLR high 5V ± 0.5V 2.5 2.5 2.5 ns
tSU Setup time Data before CLK↑ 5V ± 0.5V 4.5 4.5 4.5 ns
tH Hold time Data after CLK↑ 5V ± 0.5V 0.5 0.5 0.5 ns
tW Pulse duration CLK high or low 5V ± 0.5V 5 5 5 ns
tW Pulse duration CLR low 5V ± 0.5V 5 5 5 ns