SCLS991 November   2023 SN74AHC165

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Noise Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 125°C UNIT
MIN MAX MIN MAX
tW Pulse duration SH/LD low 3.3 V ± 0.3 V 6 7 ns
tW Pulse duration CLK high or low 3.3 V ± 0.3 V 7.5 9 ns
tSU Setup time SH/LD high before CLK↑ 3.3 V ± 0.3 V 5 6 ns
tSU Setup time SER before CLK↑ 3.3 V ± 0.3 V 5 6 ns
tSU Setup time CLK INH low before CLK↑ 3.3 V ± 0.3 V 5 5 ns
tSU Setup time CLK INH high before CLK↑ 3.3 V ± 0.3 V 5 5 ns
tSU Setup time Data before SH/LD↓ 3.3 V ± 0.3 V 7.5 8.5 ns
tH Hold time SER data after CLK↑ 3.3 V ± 0.3 V 0 0 ns
tH Hold time PAR data after SH/LD↓ 3.3 V ± 0.3 V 0.5 0.5 ns
tW Pulse duration SH/LD low 5 V ± 0.5 V 4 4 ns
tW Pulse duration CLK high or low 5 V ± 0.5 V 5 6 ns
tSU Setup time SH/LD high before CLK↑ 5 V ± 0.5 V 4 4 ns
tSU Setup time SER before CLK↑ 5 V ± 0.5 V 4 4 ns
tSU Setup time CLK INH low before CLK↑ 5 V ± 0.5 V 3.5 3.5 ns
tSU Setup time CLK INH high before CLK↑ 5 V ± 0.5 V 3.5 3.5 ns
tSU Setup time Data before SH/LD↓ 5 V ± 0.5 V 5 5 ns
tH Hold time SER data after CLK↑ 5 V ± 0.5 V 0.5 0.5 ns
tH Hold time PAR data after SH/LD↓ 5 V ± 0.5 V 1 1 ns