SCLS376J June 1997 – July 2024 SN54AHC273 , SN74AHC273
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
These devices are
positive-edge-triggered D-type
flip-flops with a
direct clear ( CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) | BODY SIZE(3) |
---|---|---|---|
SNx4AHC273 | N (PDIP, 20) | 24.33mm x 9.4mm | 25.40mm x 6.35mm |
DB (SSOP, 20) | 7.2mm × 7.8mm | 7.50mm x 5.30mm | |
NS (SOP, 20) | 12.60mm x 7.8mm | 12.6mm x 5.30mm | |
PW (TSSOP, 20) | 6.50mm × 6.4mm | 6.50mm x 4.40mm | |
DGV (TVSOP, 20) | 5.00mm x 6.4mm | 5.00mm x 4.40mm | |
DW (SOIC, 20) | 12.80mm × 10.3mm | 12.8mm x 7.5mm |