SCLS264R December   1995  – February 2024 SN54AHCT125 , SN74AHCT125

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions #GUID-C584B3C3-85AF-4F58-8781-0C1F02DBE148/SCLS2644195
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Noise Characteristics
    7. 5.7 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • BQA|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.

For the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Device Information
PART NUMBER RATING PACKAGE(1)
SN54AHCT125 Military J (CDIP, 14)
W (CFP, 14)
FK (LCCC, 20)
SN74AHCT125 Commercial D (SOIC, 14)
DB (SSOP, 14)
DGV (TVSOP, 14)
N (PDIP, 14)
NS (SOP, 14)
PW (SOP, 14)
RGY (VQFN, 14)
BQA (WQFN, 14)
(1) For more information, see Section 11.
GUID-20230612-SS0I-ZXXW-0N1H-PSFPFVD90SNW-low.png
Pin numbers are for D, DB, DGV, J, N, NS, PW, RGY, and W packages.
Logic Diagram (Positive Logic)