3 Description

The ’AHCT132 devices are quadruple positive-NAND gates. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

Package Information⁽¹⁾

PART NUMBER	PACKAGE	PACKAGE SIZE	BODY SIZE (NOM)
SN74AHCT132	D (SOIC, 14)	8.7 mm × 6 mm	8.7 mm × 3.9 mm
	DB (SSOP, 14)	6.2 mm × 7.8 mm	6.2 mm × 5.3 mm
	DGV (TVSOP, 14)	3.6 mm × 6.4 mm	3.6 mm × 4.4 mm
	N (PDIP, 14)	19.3 mm × 8 mm	19.3 mm × 6.3 mm
	NS (SOP, 14)	10.3 mm × 7.8 mm	10.3 mm × 5.3 mm
	PW (TSSOP, 14)	5 mm × 6.4 mm	5 mm × 4.4 mm
	BQA (WQFN, 14)	3 mm × 2.5 mm	3 mm × 2.5 mm
SN54AHCT132	J (CDIP, 14)	21.3 mm × 7.6 mm	19.56 mm × 6 mm
	W (CFP, 14)	9.9 mm × 6.3 mm	9.2 mm × 6.3 mm
	FK (LCCC, 20)	8.9 mm × 8.9 mm	8.9 mm × 8.9 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

(1) The package size (length × width) is a nominal value and includes pins, where applicable.

(1) The body size (length × width) is a nominal value and does not include pins.

Logic Diagram, Each Gate (Positive Logic)