SGDS023D February   2002  – October 2023 SN74AHCT14Q-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Noise Characteristics
    8. 6.8 Operating Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Typical Application
    2. 9.2 Power Supply Recommendations
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • PW|14
  • BQA|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74AHCT14Q-Q1 contains six independent inverters. This device performs the Boolean function Y = A.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM)(3)
SN74AHCT14Q-Q1 D (SOIC, 14) 8.65 mm × 6 mm 8.65 mm × 3.9 mm
PW (TSSOP, 14) 5 mm × 6.4 mm 5 mm × 4.4 mm
BQA (WQFN, 14) 3 mm × 2.5 mm 3 mm × 2.5 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable
(3) The body size (length × width) is a nominal value and does not include pins.
GUID-DC5D4F8D-F5AE-4B09-9BBE-E592CB40B8AC-low.png Logic Diagram, Each Inverter (Positive Logic)