SCLS263R December   1995  – October 2023 SN54AHCT74 , SN74AHCT74

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Noise Characteristics
    9. 6.9  Operating Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TTL-Compatible CMOS Inputs
      2. 8.3.2 Balanced CMOS Push-Pull Outputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Input Considerations
        2. 9.2.1.2 Output Considerations
        3. 9.2.1.3 Power Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • BQA|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM)(3)
SN54AHCT74 J (CDIP, 14) 21.3 mm × 7.6 mm 19.56 mm × 6.67 mm
W (CFP, 14) 13.1 mm × 6.92 mm 13.1 mm × 6.92 mm
FK (LCCC, 20) 8.9 mm × 8.9 mm 8.9 mm × 8.9 mm
SN74AHCT74 N (PDIP , 14) 19.3 mm × 8 mm 19.3 mm × 6.35 mm
D (SOIC, 14) 8.7 mm × 6 mm 8.7 mm × 3.91 mm
NS (SOP, 14) 10.3 mm × 7.8 mm 10.3 mm × 5.3 mm
DB (SSOP, 14) 6.2 mm × 7.8 mm 6.2 mm × 5.3 mm
PW (TSSOP, 14) 5 mm × 6.4 mm 5 mm × 4.4 mm
DGV (TVSOP, 14) 3.6 mm × 6.4 mm 3.6 mm × 4.4 mm
RGY (VQFN, 14) 3.5 mm × 3.5 mm 3.50 mm × 3.50 mm
BQA (WQFN, 14) 3 mm × 2.5 mm 3.00 mm × 2.50 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
GUID-8F1527F6-67EE-40AB-BA1A-B7516665109A-low.gif Logic Diagram, Each Flip-Flop (Positive Logic)