SCES383L March   2002  – January 2018 SN74AUC1G126

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Logic Diagram (Positive Logic)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: CL = 15 pF
    7. 6.7 Switching Characteristics: CL = 30 pF
    8. 6.8 Operating Characteristics
  7. 7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Balanced CMOS Push-Pull Outputs
      2. 9.3.2 Standard CMOS Inputs
      3. 9.3.3 Negative Clamping Diodes
      4. 9.3.4 Special Features
        1. 9.3.4.1 Partial Power Down (Ioff)
        2. 9.3.4.2 Overvoltage Tolerant Inputs
        3. 9.3.4.3 Output Enable
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
  • DCK|5
  • YZP|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators that have the following characteristics:

  • PRR ≤ 10 MHz
  • ZO = 50 Ω

SN74AUC1G126 sces383_load_circuit.gif
1. CL includes probe and jig capacitance.
Figure 9. Load Circuit

Table 1. Loading Conditions for Parameter

TEST S1
tPLH (1), tPHL (1) Open
tPLZ (2), tPZL (3) 2 × VCC
tPHZ (2), tPZH (3) GND

Table 2. Loading Conditions for VCC

VCC CL RL VΔ
0.8 V 15 pF 2 kΩ 0.1 V
1.2 V ± 0.1 V 15 pF 2 kΩ 0.1 V
1.5 V ± 0.1 V 15 pF 2 kΩ 0.1 V
1.8 V ± 0.15 V 15 pF 2 kΩ 0.15 V
2.5 V ± 0.2 V 15 pF 2 kΩ 0.15 V
1.8 V ± 0.15 V 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V 30 pF 500 kΩ 0.15 V
SN74AUC1G126 sces383_voltage_waveforms_pulse_duration.gifFigure 10. Voltage Waveforms: Pulse Duration
SN74AUC1G126 sces383_voltage_waveforms_propagation_delay_times_inverting_and_non_inverting_outputs.gif
1. All outputs are measured one at a time, with one transition per measurement.
Figure 11. Voltage Waveforms: Propagation Delay Times, Inverting and Noninverting Outputs
SN74AUC1G126 sces383_voltage_waveforms_setup_and_hold_times.gifFigure 12. Voltage Waveforms: Setup and Hold Times
SN74AUC1G126 sces383_voltage_waveforms_enable_and_disable_times_low_and_high_level_enabling.gif
1. Waveform 1 is for an output with internal conditions such as the output is low, except when disabled by the output control.
2. Waveform 2 is for an output with internal conditions such as the output is high, except when disabled by the output control.
3. All outputs are measured one at a time, with one transition per measurement.
Figure 13. Voltage Waveforms: Enable and Disable Times, Low- and High-Level Enabling