SCES644D MARCH   2006  – December 2015 SN74AUP1G74

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, TA = 25°C
    6. 6.6  Electrical Characteristics, TA = -40°C to +85°C
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics, CL = 5 pF
    9. 6.9  Switching Characteristics, CL = 10 pF
    10. 6.10 Switching Characteristics, CL = 15 pF
    11. 6.11 Switching Characteristics, CL = 30 pF
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information 
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width)
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Power Button Circuit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74AUP1G74 can be used to control a power button input. Tying Q to D will switch the output between high and low each time that a high signal is sent to CLK from the push button.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin must be connected directly to VCC to be inactive.

9.2 Typical Power Button Circuit

SN74AUP1G74 sces644_app1.gif Figure 5. Device Power Button Circuit

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions must be considered to prevent ringing.

9.2.2 Detailed Design Procedure

  1. Recommended Input Conditions:
  2. Recommend Output Conditions:
    • Series resistors on the output may be used if the user desires to slow the output edge signal or limit the output current.

9.2.3 Application Curve

SN74AUP1G74 excel_ces644.gif
AUP1G08 data at CL = 15 pF
Figure 6. Switching Characteristics at 25 MHz