SCES852A December   2013  – April 2016 SN74AUP1T34-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 AC Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fully Configurable Dual-Rail Design
      2. 8.3.2 Partial-Power-Down Mode Operation
      3. 8.3.3 VCC Isolation
      4. 8.3.4 Input Hysteresis
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The SN74AUP1T34-Q1 is a unidirectional, single-bit, dual-supply, noninverting voltage-level translator. Pin A, which is referenced to VCCA, receives the signal that is to be level translated. Pin B, which is referenced to VCCB, transmits the level translated signal. Both supply pins VCCA and VCCB support a voltage range from 0.9 V to
3.6 V.

8.2 Functional Block Diagram

SN74AUP1T34-Q1 SN74AUP1T34-Q1_Functional_Block_Diagram.gif

8.3 Feature Description

8.3.1 Fully Configurable Dual-Rail Design

Both VCCA and VCCB can be supplied at any voltage from 0.9 V to 3.6 V, making the device suitable for translating between any of the voltage nodes (1 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).

8.3.2 Partial-Power-Down Mode Operation

Ioff circuitry disables the outputs, preventing damaging current backflow through the SN74AUP1T34-Q1 when it is powered down. This can occur in applications where subsections of a system are powered down (partial-power-down) to reduce power consumption.

8.3.3 VCC Isolation

The VCC isolation feature ensures that if either VCCA or VCCB are at GND (or < 0.4 V), both ports A and B are set to a high-impedance state, preventing false logic levels from being presented to either bus.

8.3.4 Input Hysteresis

Input hysteresis allows the input to support slew rates as slow as 200 ns/V, improving switching noise immunity.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SN74AUP1T34-Q1.

Table 1. Function Table

INPUT OUTPUT
A PORT B PORT
L L
H H