SCES693H February   2008  – March 2024 SN74AVC4T774

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics: VCCA = 1.2 V ± 0.1 V
    7. 5.7  Switching Characteristics: VCCA = 1.5 V ± 0.1 V
    8. 5.8  Switching Characteristics: VCCA = 1.8 V ± 0.15 V
    9. 5.9  Switching Characteristics: VCCA = 2.5 V ± 0.2 V
    10. 5.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.1V to 3.6V Power-Supply Range
      2. 7.3.2 Support High-Speed Translation
      3. 7.3.3 Ioff Supports Partial-Power-Down Mode Operation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 10 MHz
  • ZO = 50 Ω
  • Δt/ΔV ≤ 1 ns/V

GUID-3D71EDC8-E56A-4C89-B036-A6A0F5521780-low.gif
A. CL includes probe and jig capacitance.
Figure 6-1 Load Circuit
Table 6-1 Load Circuit Parameters
Test Parameter S1
tpd Propagation (delay) time Open
tPZL, tPLZ Enable time, disable time 2 × VCCO
tPZH, tPHZ Enable time, disable time GND
Table 6-2 Load Circuit Conditions
VCCO RL CL VTP
1.2 V ± 0.1 V 2 kΩ 15 pF 0.1 V
1.5 V ± 0.1 V 2 kΩ 15 pF 0.1 V
1.8 V ± 0.15 V 2 kΩ 15 pF 0.15 V
2.5 V ± 0.2 V 2 kΩ 15 pF 0.15 V
3.3 V ± 0.3 V 2 kΩ 15 pF 0.3 V
GUID-7E33DD80-46DD-4180-B7F4-94678A8F0930-low.gif
  1. VCCI is the VCC associated with the input port.
  2. VCCO is the VCC associated with the output port.
  3. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1.
  4. tPLH and tPHL are the same as tpd.
  5. The outputs are measured one at a time, with one transition per measurement.
Figure 6-2 Propagation Delay
GUID-76FAEEB1-24EC-4ECD-9E88-9F54DEED822D-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1.
Figure 6-3 Input Transition Rise and Fall Rate
GUID-50672978-A39C-4114-96BF-0BE989AE07C7-low.gif
A. Output waveform on the condition that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
Figure 6-4 Enable Time And Disable Time