SCES785E December   2008  – November 2023 SN74AVC8T245-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics: VCCA = 1.2 V
    7. 5.7  Switching Characteristics: VCCA = 1.5 V ± 0.1 V
    8. 5.8  Switching Characteristics: VCCA = 1.8 V ± 0.15 V
    9. 5.9  Switching Characteristics: VCCA = 2.5 V ± 0.2 V
    10. 5.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Total Static Current Consumption (ICCA + ICCB)
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design
      2. 7.3.2 Supports High Speed Translation
      3. 7.3.3 Ioff Supports Partial-Power-Down Mode Operation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHL|24
  • PW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74AVC8T245-Q1 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The SN74AVC8T245-Q1 operation is optimal with VCCA and VCCB set at
1.4 V to 3.6 V. It is operational with VCCA and VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC8T245-Q1 design enables asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. One can use the output-enable (OE) input to disable the outputs so the buses are effectively isolated.

In the SN74AVC8T245-Q1 design, VCCA supplies the control pins (DIR and OE).

This device specification covers partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The VCC isolation feature allows both ports to be in the high-impedance state if either VCC input is at GND.

To put the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
SN74AVC8T245-Q1 RHL (VQFN, 24) 5.5 mm × 3.5 mm
PW (TSSOP, 24) 7.8 mm × 6.4 mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-8B34AE3D-54BF-4FBA-82DD-7C61ED2D3B24-low.gif Logic Diagram (Positive Logic)