SCES901D February   2019  – January 2024 SN74AXC1T45-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Operating Characteristics: TA = 25°C
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Standard CMOS Inputs
      2. 7.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 7.3.3 Partial Power Down (Ioff)
      4. 7.3.4 VCC Isolation
      5. 7.3.5 Over-voltage Tolerant Inputs
      6. 7.3.6 Negative Clamping Diodes
      7. 7.3.7 Fully Configurable Dual-Rail Design
      8. 7.3.8 I/Os with Integrated Static Pull-Down Resistors
      9. 7.3.9 Supports High-Speed Translation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Enable Times
    2. 8.2 Typical Applications
      1. 8.2.1 Interrupt Request Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Universal Asynchronous Receiver-Transmitter (UART) Interface Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCK|6
  • DRY|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC-Q100 qualified for automotive applications
  • Fully configurable dual-rail design allows each port to operate with a power supply range from 0.65V to 3.6V
  • Operating temperature: –40°C to +125°C
  • Glitch-free power supply sequencing
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature
    • If Either VCC input is below 100mV, all I/O outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V Human body model
    • 1000-V Charged-device model