SCES882E December   2017  – December 2023 SN74AXC1T45

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics: TA = 25°C
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 0.65-V to 3.6-V Power-Supply Range
      2. 7.3.2 I/Os with Integrated Static Pull-Down Resistors
      3. 7.3.3 Support High-Speed Translation
      4. 7.3.4 Ioff Supports Partial-Power-Down Mode Operation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Enable Times
    2. 8.2 Typical Applications
      1. 8.2.1 Unidirectional Logic Level-Shifting Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bidirectional Logic Level-Shifting Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Up Considerations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 1 MHz
  • ZO = 50 Ω
  • dv/dt ≤ 1 ns/V

GUID-7E389BE0-ED00-4583-9437-3CF9C05B46C4-low.gif
A. CL includes probe and jig capacitance.
Figure 6-1 Load Circuit
Table 6-1 Load Circuit Conditions
ParameterVCCORLCLS1VTP
Δt/ΔvInput transition rise or fall rate0.65 V – 3.6V1MΩ15pFOpenN/A
tpdPropagation (delay) time1.1V – 3.6V2kΩ15pFOpenN/A
0.65 V – 0.95 V20kΩ15pFOpenN/A
ten, tdisEnable time, disable time3V – 3.6V2kΩ15pF2 × VCCO0.3V
1.65 V – 2.7V2kΩ15pF2 × VCCO0.15 V
1.1V – 1.6V2kΩ15pF2 × VCCO0.1V
0.65 V – 0.95 V20kΩ15pF2 × VCCO0.1V
ten, tdisEnable time, disable time3V – 3.6V2kΩ15pFGND0.3V
1.65 V – 2.7V2kΩ15pFGND0.15 V
1.1V – 1.6V2kΩ15pFGND0.1V
0.65 V – 0.95 V20kΩ15pFGND0.1V
GUID-8FB7C7AF-0FEB-4776-A6BF-8CB9B9015B40-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-2 Propagation Delay
GUID-BEFDD9FE-47FF-4F0B-AF7A-C3835E0EA415-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-3 Input Transition Rise or Fall Rate
GUID-2F696A6A-EA78-4C44-9A56-2F234FC70BDE-low.gif
  1. Illustrative purposes only. Enable Time is a calculation as described in the data sheet.
  2. Output waveform on the condition that input is driven to a valid Logic Low.
  3. Output waveform on the condition that input is driven to a valid Logic High.
  4. VCCI is the supply pin associated with the input port
  5. VCCO is the supply pin associated with the output port.
  6. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-4 Disable and Enable Time