SCES918E February   2020  – January 2024 SN74AXC4T774-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 0.7 ± 0.05V
    7. 5.7  Switching Characteristics, VCCA = 0.8 ± 0.04V
    8. 5.8  Switching Characteristics, VCCA = 0.9 ± 0.045V
    9. 5.9  Switching Characteristics, VCCA = 1.2 ± 0.1V
    10. 5.10 Switching Characteristics, VCCA = 1.5 ± 0.1V
    11. 5.11 Switching Characteristics, VCCA = 1.8 ± 0.15V
    12. 5.12 Switching Characteristics, VCCA = 2.5 ± 0.2V
    13. 5.13 Switching Characteristics, VCCA = 3.3 ± 0.3V
    14. 5.14 Operating Characteristics: TA = 25°C
    15. 5.15 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Standard CMOS Inputs
      2. 7.3.2  Balanced High-Drive CMOS Push-Pull Outputs
      3. 7.3.3  Partial Power Down (Ioff)
      4. 7.3.4  VCC Isolation
      5. 7.3.5  Over-voltage Tolerant Inputs
      6. 7.3.6  Glitch-free Power Supply Sequencing
      7. 7.3.7  Negative Clamping Diodes
      8. 7.3.8  Fully Configurable Dual-Rail Design
      9. 7.3.9  I/Os with Integrated Static Pull-Down Resistors
      10. 7.3.10 Supports High-Speed Translation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 1MHz
  • ZO = 50Ω
  • dv/dt ≤ 1ns/V

GUID-479AFFA3-7B2D-4485-83E1-DE578BD03865-low.gif
A. CL includes probe and jig capacitance.
Figure 6-1 Load Circuit
Table 6-1 Load Circuit Conditions
ParameterVCCORLCLS1VTP
Δt/ΔvInput transition rise or fall rate0.65V – 3.6V1MΩ15pFOpenN/A
tpdPropagation (delay) time1.1V – 3.6V2kΩ15pFOpenN/A
0.65V – 0.95V20kΩ15pFOpenN/A
ten, tdisEnable time, disable time3V – 3.6V2kΩ15pF2 × VCCO0.3V
1.65V – 2.7V2kΩ15pF2 × VCCO0.15V
1.1V – 1.6V2kΩ15pF2 × VCCO0.1V
0.65V – 0.95V20kΩ15pF2 × VCCO0.1V
ten, tdisEnable time, disable time3V – 3.6V2kΩ15pFGND0.3V
1.65V – 2.7V2kΩ15pFGND0.15V
1.1V – 1.6V2kΩ15pFGND0.1V
0.65V – 0.95V20kΩ15pFGND0.1V
GUID-1B7C535C-3793-48CB-B4FC-F1FDCC5DE3CC-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-2 Propagation Delay
GUID-ABBEA988-9BE7-47BC-BA1B-9E9063E8C096-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-3 Input Transition Rise or Fall Rate
GUID-98595081-30A5-4627-A655-C2433B1B67BD-low.gif
A. Output waveform on the condition that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 6-4 Enable Time And Disable Time