SCDS192C
April 2005 – September 2021
SN74CBTU4411
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristic
7
Parameter Measurement Information
7.1
Enable and Disable Times
7.2
Skew and Propagation Delay Times
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
13
Electrostatic Discharge Caution
14
Glossary
15
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
ZST|72
MPBG455C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
scds192c_oa
scds192c_pm
1
Features
Supports SSTL_18 signaling levels
Suitable for DDR-II applications
D-port outputs are precharged by bias voltage (V
BIAS
)
Internal termination for control inputs
High bandwidth (400 MHz minimum)
Low and flat ON-state resistance (r
on
) characteristics, (r
on
= 17 Ω maximum)
Internal 400-Ω pulldown resistors
Low differential and rising or falling edge skew
Latch-up performance exceeds 100 mA per JESD 78, Class II