SCDS192C April   2005  – September 2021 SN74CBTU4411

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristic
  7. 7 Parameter Measurement Information
    1. 7.1 Enable and Disable Times
    2. 7.2 Skew and Propagation Delay Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Electrostatic Discharge Caution
  14. 14Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Overview

The SN74CBTU4411 device is organized as an 11-bit 1-of-4 multiplexer or demultiplexer with a single switch-enable (EN) input. When EN is low, the switch is enabled and the H port is connected to one of the D ports. Ports D0 to D9 for the disabled channels are connected to VBIAS through a 400-Ω resistor. DQS_EN determines the output voltage for the disabled D10 ports. When DQS_EN is low, this voltage is VBIAS. When DQS_EN is high, the disabled D10 ports are connected to an internal voltage (VBIAS_DQS) source, which is approximately equal to 0.7 VDD.

When EN is high, all the channels are disabled. Ports D0 to D9 are connected to VBIAS. For the D10 port, the disabled output voltage is determined by the DQS_EN input. When DQS_EN is low, this voltage is VBIAS. When DQS_EN is high, this voltage is VDD.