SCLS107G December   1982  – October 2021 SN54HC138 , SN74HC138

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings: SN74HC138
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: SN74HC138
    5. 6.5  Thermal Information: SN54HC138
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics: SN74HC138
    8. 6.8  Electrical Characteristics: SN54HC138
    9. 6.9  Switching Characteristics
    10. 6.10 Switching Characteristics: SN74HC138
    11. 6.11 Switching Characteristics: SN54HC138
    12. 6.12 Typical Characteristic
  7. 7 Parameter Measurement Information
    1.     21
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • PW|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN74HC138D SOIC (16) 9.90 mm x 3.90 mm
SN74HC138DB SSOP (16) 6.20 mm x 5.30 mm
SN74HC138N PDIP (16) 19.32 mm x 6.35 mm
SN74HC138NS SO (16) 10.20 mm x 5.30 mm
SN74HC138PW TSSOP (16) 5.00 mm x 4.40 mm
SN54HC138J CDIP (16) 21.34 mm x 6.92 mm
SN54HC138W CFP (16) 10.16 mm x 6.73 mm
SN54HC138FK LCCC (20) 8.89 mm x 8.89 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
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Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.

Functional Block DIagram