SCLS543C September   2002  – June 2022 SN74HC244-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74HC244 is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN74HC244QDW-Q1 SOIC (20) 12.80 mm × 7.50 mm
SN74HC244QPW-Q1 TSSOP (20) 6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-19EE75CB-0D07-43B6-BF3D-C3F51D3DB61D-low.gif Functional Block Diagram