SCLS308E January   1996  – March 2022 SN54HC365 , SN74HC365

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The SNx4HC365 contains six independent buffers with 3-state outputs. All channels are placed into the high-impedance mode when either of the output enable (OE) pins are set to the high state.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN54HC365J CDIP (16) 24.38 mm × 6.92 mm
SN74HC365D SOIC (16) 9.90 mm × 3.90 mm
SN74HC365N PDIP (16) 19.31 mm × 6.35 mm
SN74HC365NS SO (16) 6.20 mm × 5.30 mm
SN74HC365PW TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20210218-CA0I-5KGK-KS7K-SSMRQLFC6H7G-low.gif Functional Block Diagram