SCLS325K March   1996  – February 2024 SN74HC4066

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DB|14
  • PW|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Operating Characteristics

VCC = 4.5V, TA = 25°C
PARAMETERTEST CONDITIONSTYPUNIT
CpdPower dissipation capacitance per gateCL = 50pF,f = 1MHz45pF
Minimum through bandwidth, A to B or B to A(1) [20 log (VO / VI)] = –3 dBCL = 50pF,
VC = VCC		RL = 600 Ω,
(see Figure 6-8)

100

MHz
Crosstalk between any switches(2)CL = 10pF,
fin = 1MHz		RL = 50 Ω,
(see Figure 6-9)		-45dB
Feed through, switch off, A to B or B to A(2)CL = 50pF,
fin = 1MHz		RL = 600 Ω,
(see Figure 6-10)		-42dB
Amplitude distortion rate, A to B or B to ACL = 50pF,
fin = 1kHz		RL = 10kΩ,
(see Figure 6-11)		0.05%
(1) Adjust the input amplitude for output = 0 dBm at f = 1MHz. Input signal must be a sine wave.
(2) Adjust the input amplitude for input = 0 dBm at f = 1MHz. Input signal must be a sine wave.