SCLS826D August   2020  – December 2021 SN74HCS165-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     4
    2.     5
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 CMOS Schmitt-Trigger Inputs
      3. 8.3.3 Clamp Diode Structure
      4. 8.3.4 Latching Logic
      5. 8.3.5 Wettable Flanks
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Characteristics

CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
PARAMETER VCC Operating free-air temperature (TA) UNIT
25°C –40°C to 125°C
MIN MAX MIN MAX
fclock Clock frequency 2 V 49 43 MHz
4.5 V 130 120
6 V 170 150
tw Pulse duration
SH/LD low
 		 2 V 6 7 ns
4.5 V 6 7
6 V 6 7

CLK high or low

 2 V 7 11
4.5 V 6 7
6 V 6 7

tsu
 
Setup time

 SH/LD high before CLK↑ 2 V 13 21 ns
4.5 V 5 7
6 V 4 6

SER before CLK↑

 2 V 8 14
4.5 V 4 6
6 V 4 6

CLK INH low before CLK↑

 2 V 6 9
4.5 V 4 5
6 V 4 5

CLK INH high before CLK↑

 2 V 6 9
4.5 V 4 5
6 V 4 5
Data before SH/LD↑ 2 V 9 17
4.5 V 4 6
6 V 4 6

th
 
Hold time
Ser data after CLK↑

 2 V 0 0 ns
4.5 V 0 0
6 V 0 0
PAR data after SH/LD↑ 2 V 5 6
4.5 V 4 5
6 V 3 4
SH/LD high after CLK↑ 2 V 0 0
4.5 V 0 0
6 V 0 0