SCLS065G November   1988  – October 2022 SN74HCT02

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • PW|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

These devices contain four independent 2-input NOR gates. They perform the Boolean function Y = A • B or Y = A + B in positive logic.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HCT02D SOIC (14) 8.65 mm × 3.90 mm
SN74HCT02N PDIP (14) 19.31 mm × 6.35 mm
SN74HCT02NSR SO (14) 10.20 mm × 5.30 mm
SN74HCT02PW TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-6256DE58-0156-424F-90BB-133B572276BF-low.png Functional Block Diagram