SCLS066E March   1982  – August 2022 SN74HCT139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Rating
    2. 6.2 Recommended Operating Conditions (1)
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Operating Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • PW|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The ’HCT139 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times.

Device Information(1)
ORDERABLE PART NUMBER PACKAGE† BODY SIZE (NOM)
SN74HCT139 N (PDIP, 16) 19.31 mm × 6.35 mm
D (SOIC, 16) 9.90 mm × 3.90 mm
DB (SSOP, 16) 6.2 mm x 5.3 mm
PW (TSSOP, 16) 5.00 mm × 4.40 mm
SNJ54HCT139 J (CDIP, 16) 24.38 mm × 6.92 mm
W (CFP, 16) 10.3 mm x 1.65 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20220401-SS0I-23FZ-D7PM-TGRSRSHMSR2T-low.png
A. Pin numbers shown are for the D, DB, J, N, PW, and W packages.
Logic Diagram (Positive Logic)