SCLS068G November   1988  – July 2022 SN74HCT273

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions (1)
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|20
  • NS|20
  • N|20
  • DW|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HCT273DW SOIC (20) 12.80 mm × 7.50 mm
SN74HCT273DB SSOP (20) 7.20 mm × 5.30 mm
SN74HCT273N PDIP (20) 25.40 mm × 6.35 mm
SN74HCT273NS SO (20) 15.00 mm × 5.30 mm
SN74HCT273PW TSSOP (20) 6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20211008-SS0I-LMSL-BK6X-FDVB1FS6FWXF-low.png Logic Diagram, (postive logic)
GUID-89C6A0B4-A882-4A2F-9624-279EB1B9F772-low.gif Logic Diagram, Each Flip Flop (positive logic)