SCLS005E March   1984  – February 2022 SN54HCT374 , SN74HCT374

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|20
  • NS|20
  • N|20
  • DW|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the ’HCT374 devices are edge-triggered D-type flip-flops. On the positive transition ofthe clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.

An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN74HCT374DW SOIC (20) 12.80 mm × 7.50 mm
SN74HCT374DB SSOP (20) 7.20 mm × 5.30 mm
SN74HCT374N PDIP (20) 25.40 mm × 6.35 mm
SN74HCT374NS SO (20) 15.00 mm × 5.30 mm
SN74HCT374PW TSSOP (20) 6.50 mm × 4.40 mm
SN54HCT374J CDIP (20) 26.92 mm × 6.92 mm
SNJ54HCT374FK LCCC (20) 8.89 mm × 8.45 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20211013-SS0I-H8W9-TKKH-JQRH7BL46N2Q-low.pngFunctional Block Diagram