SCLS883A October   2021  – December 2021 SN74HCT595-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8.     14
    9. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 Balanced CMOS 3-State Outputs
      2. 8.2.2 Balanced CMOS Push-Pull Outputs
      3. 8.2.3 TTL-Compatible CMOS Inputs
      4. 8.2.4 Latching Logic
      5. 8.2.5 Clamp Diode Structure
    3. 8.3 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS TA = 25°C -40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX
VOH High-level output voltage VI = VIH or VIL IOH = -20 uA, VCC = 4.5 V 4.4 4.4 V
IOH = -6 mA, VCC = 4.5 V 3.98 3.84 V
VOL Low-level output voltage VI = VIH or VIL IOL = 20 uA, VCC = 4.5 V 0.1 0.1 V
IOL = 6 mA, VCC = 4.5 V 0.26 0.33 V
II Input leakage current VI = VCC or 0 VCC = 5.5 V ±100 ±1000 nA
IOZ Off-State (High-Impedance State) Output Current VO = VCC or 0, QA-QH VCC = 5.5 V ±0.5 ±5 µA
ICC Supply current VI = VCC or 0, IO = 0 VCC = 5.5 V 8 80 µA
ΔICC Additional Quiescent Device Current Per Input Pin VI = VCC - 2.1V VCC = 4.5V to 5.5V 126.2 157.5 µA
VI = 0.5 V or 2.4V VCC = 5.5V 2.4 2.9 mA
Ci Input capacitance VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V 10 pF
CO Output capacitance VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V 20 pF
Cpd Power dissipation capacitance per gate No load 50 pF