SCLS880A October   2021  – December 2021 SN74HCT595

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8.     14
    9. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 Balanced CMOS 3-State Outputs
      2. 8.2.2 Balanced CMOS Push-Pull Outputs
      3. 8.2.3 TTL-Compatible CMOS Inputs
      4. 8.2.4 Latching Logic
      5. 8.2.5 Clamp Diode Structure
    3. 8.3 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

GUID-911E7D28-C7C6-4805-B7BB-27F979912AB9-low.gif
(1) CL includes probe and test-fixture capacitance.
Figure 7-1 Load Circuit for 3-State Outputs
GUID-BFFF0460-44C8-4CEE-AD5B-31662BDFF909-low.gifFigure 7-3 Voltage Waveforms, Pulse Duration
GUID-0C974BC2-D67A-48AD-9F4F-4F68FB5355CD-low.gif
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-5 Voltage Waveforms Propagation Delays
GUID-C6D867FF-EEAD-472D-9E21-B2F1CFFA08AA-low.gif
(1) The greater between tr and tf is the same as tt.
Figure 7-7 Voltage Waveforms, Input and Output Transition Times
GUID-2621FE8E-5E3B-4302-9AD0-E043E1971DB8-low.gif
(1) CL includes probe and test-fixture capacitance.
Figure 7-2 Load Circuit for Push-Pull Outputs
GUID-FFDD3B0A-BDE6-483C-BB7C-170803B317F1-low.gifFigure 7-4 Voltage Waveforms, Setup and Hold Times
GUID-ACA9CA80-B2AF-49B8-A417-D345DC38AEF5-low.gifFigure 7-6 Voltage Waveforms Propagation Delays