SCLS169G december   1982  – october 2022 SN54HCT74 , SN74HCT74

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Revision History
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Power Supply Recommendations
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DB|14
  • PW|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

GUID-20654E66-970D-45DC-A270-8C43E6874C69-low.gif
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for Push-Pull Outputs
GUID-20201229-CA0I-BXWT-Q7X9-JDBSDCQHTBQJ-low.gifFigure 6-2 Voltage Waveforms, TTL-Compatible CMOS Inputs Pulse Duration
GUID-20201229-CA0I-PGLG-HN2B-WVRKFTLXGRL1-low.gif
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4 Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
GUID-20201229-CA0I-XKVX-WCDW-19X6NBQ8QMNT-low.gifFigure 6-3 Voltage Waveforms, TTL-Compatible CMOS Inputs Setup and Hold Times