SDLS049C December   1983  – November 2016 SN5414 , SN54LS14 , SN7414 , SN74LS14

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
      1. 6.7.1 SNx414 Circuits
      2. 6.7.2 SNx4LS14 Circuits
  7. 7 Parameter Measurement Information
    1. 7.1 Series SN5414 and SN7414 Devices
    2. 7.2 Series SN54LS14 and SN74LS14 Devices
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DB|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

7.1 Series SN5414 and SN7414 Devices

SN5414 SN54LS14 SN7414 SN74LS14 54-74-Load-Circuit-2-State-Totem.gif Figure 14. Load Circuit For
2-State Totem-Pole Outputs
SN5414 SN54LS14 SN7414 SN74LS14 54-74-Load-Circuit-3-State-Outputs.gif Figure 16. Load Circuit For 3-State Outputs
SN5414 SN54LS14 SN7414 SN74LS14 54-74-Voltage-Waveforms-Setup-Hold-Times.gif Figure 18. Voltage Waveforms
Setup and Hold Times
SN5414 SN54LS14 SN7414 SN74LS14 54-74-Load-Circuit-Open-Collector-Outputs.gif Figure 15. Load Circuit For
Open-Collector Outputs
SN5414 SN54LS14 SN7414 SN74LS14 54-74-Voltage-Waveforms-Pulse-Durations.gif Figure 17. Voltage Waveforms Pulse Durations
SN5414 SN54LS14 SN7414 SN74LS14 54-74-Voltage-Waveforms-Prop-Delay-Times.gif Figure 19. Voltage Waveforms
Propagation Delay Times
SN5414 SN54LS14 SN7414 SN74LS14 54-74-Voltage-Waves-Enable-Disable-3-State-Outputs.gif
A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω ; tr and tf ≤ 7 ns for Series SN5414 and SN7414 devices and tr and tf ≤ 2.5 ns for Series SN54S14 and SN74S14 devices.
F. The outputs are measured one at a time with one input transition per measurement.
Figure 20. Voltage Waveforms Enable and Disable Times, 3-State Outputs

7.2 Series SN54LS14 and SN74LS14 Devices

SN5414 SN54LS14 SN7414 SN74LS14 54LS-74LS-Load-Circuit-2-State-Totem.gif Figure 21. Load Circuit For
2-State Totem-Pole Outputs
SN5414 SN54LS14 SN7414 SN74LS14 54LS-74LS-Load-Circuit-3-State-Outputs.gif Figure 23. Load Circuit For 3-State Outputs
SN5414 SN54LS14 SN7414 SN74LS14 54LS-74LS-Voltage-Waveforms-Setup-Hold-Times.gif Figure 25. Voltage Waveforms
Setup and Hold Times
SN5414 SN54LS14 SN7414 SN74LS14 54LS-74LS-Load-Circuit-Open-Collector-Outputs.gif Figure 22. Load Circuit For
Open-Collector Outputs
SN5414 SN54LS14 SN7414 SN74LS14 54LS-74LS-Voltage-Waveforms-Pulse-Durations.gif Figure 24. Voltage Waveforms Pulse Durations
SN5414 SN54LS14 SN7414 SN74LS14 54LS-74LS-Voltage-Waveforms-Prop-Delay-Times.gif Figure 26. Voltage Waveforms
Propagation Delay Times
SN5414 SN54LS14 SN7414 SN74LS14 54LS-74LS-Voltage-Waveforms-Enable-Disable.gif
A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
Figure 27. Voltage Waveforms Enable and Disable Times, 3-State Outputs