SCLS395N April   1998  – March 2023 SN74LV138A

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions (1)
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCC = 2.5 V ± 0.25 V
    7. 6.7  Switching Characteristics, VCC = 3.3 V ± 0.3 V
    8. 6.8  Switching Characteristics, VCC = 5 V ± 0.5 V
    9. 6.9  Operating Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Standard CMOS Inputs
      2. 8.3.2 Balanced CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Power Considerations
      2. 9.2.2 Input Considerations
      3. 9.2.3 Output Considerations
      4. 9.2.4 Detailed Design Procedure
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • DB|16
  • PW|16
  • NS|16
  • RGY|16
  • D|16
  • DGV|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74LV138A device is 3-line to 8-line decoders/demultiplexers designed for 2 V to 5.5 V VCC operation.

The conditions at the binary-select inputs (A0, A1, A2) and the three enable inputs (G2, G0, G1) select one of eight output lines. The two active-low (G0, G1) and one active-high (G2) enable inputs reduce the need for external gates or inverters when expanding.

Package Information
PART NUMBER PACKAGE(1) BODY SIZE
SN74LV138A D (SOIC, 16) 9.90 mm × 3.91 mm
DB (SSOP, 16) 6.20 mm × 5.30 mm
DGV (TVSOP, 16) 3.60 mm × 4.40 mm
NSA (BGA, 16) 2.00 mm × 2.00 mm
PW (TSSOP, 16) 5.00 mm × 4.40 mm
RGY (VQFN, 16) 4.00 mm × 3.50 mm

BQB (WQFN, 16)

3.60 mm × 2.60 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20210723-CA0I-1CJ3-MQFG-1GVMRTBQ6B2P-low.gif Logic Diagram (Positive Logic)