SCLS403K April   1998  – March 2023 SN74LV164A

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: VCC = 2.5 V ± 0.2 V
    7. 6.7  Timing Requirements: VCC = 3.3 V ± 0.3 V
    8. 6.8  Timing Requirements: VCC = 5 V ± 0.5 V
    9. 6.9  Switching Characteristics: VCC = 2.5 V ± 0.2 V
    10. 6.10 Switching Characteristics: VCC = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics: VCC = 5 V ± 0.5 V
    12. 6.12 Noise Characteristics
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • BQA|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4 Device Functional Modes

Table 8-1 Function Table(1)(2)
INPUTSOUTPUTS
CLRCLKABQAQB...QH
LXXXLLL
HLXXQA0QB0QH0
H↑HHHQAnQGn
H↑LXLQAnQGn
H↑XLLQAnQGn
(1) QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established.
(2) QAn, QGn = the level of QA or QG before the most recent ↑ transition of the clock: indicates a 1-bit shift.