SCLS916 may   2023 SN74LV2T74-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Characteristics 1.8-V VCC
    7. 6.7  Timing Characteristics 2.5-V VCC
    8. 6.8  Timing Characteristics 3.3-V VCC
    9. 6.9  Timing Characteristics 5-V VCC
    10. 6.10 Switching Characteristics 1.8-V VCC
    11. 6.11 Switching Characteristics 2.5-V VCC
    12. 6.12 Switching Characteristics 3.3-V VCC
    13. 6.13 Switching Characteristics 5-V VCC
    14. 6.14 Noise Characteristics
    15. 6.15 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Clamp Diode Structure
      3. 8.3.3 LVxT Enhanced Input Voltage
        1. 8.3.3.1 Down Translation
        2. 8.3.3.2 Up Translation
      4. 8.3.4 Wettable Flanks
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Input Considerations
        2. 9.2.1.2 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3.2 Up Translation

Input signals can be up translated using the SN74LV2T74-Q1. The voltage applied at VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0 V in the LOW state.

The inputs have reduced thresholds that allow for input HIGH state levels which are much lower than standard values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V. For the SN74LV2T74-Q1, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a typical 2.5-V to 5-V signals.

As shown in Figure 8-4, ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower than VIL(MAX).

Up Translation Combinations are as follows:

  • 1.8-V VCC – Inputs from 1.2 V
  • 2.5-V VCC – Inputs from 1.8 V
  • 3.3-V VCC – Inputs from 1.8 V and 2.5 V
  • 5.0-V VCC – Inputs from 2.5 V and 3.3 V

GUID-79218250-73F2-481D-9DF1-825AC9B58913-low.gifFigure 8-4 LVxT Up and Down Translation Example