SCLS916 may   2023 SN74LV2T74-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Characteristics 1.8-V VCC
    7. 6.7  Timing Characteristics 2.5-V VCC
    8. 6.8  Timing Characteristics 3.3-V VCC
    9. 6.9  Timing Characteristics 5-V VCC
    10. 6.10 Switching Characteristics 1.8-V VCC
    11. 6.11 Switching Characteristics 2.5-V VCC
    12. 6.12 Switching Characteristics 3.3-V VCC
    13. 6.13 Switching Characteristics 5-V VCC
    14. 6.14 Noise Characteristics
    15. 6.15 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Clamp Diode Structure
      3. 8.3.3 LVxT Enhanced Input Voltage
        1. 8.3.3.1 Down Translation
        2. 8.3.3.2 Up Translation
      4. 8.3.4 Wettable Flanks
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Input Considerations
        2. 9.2.1.2 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20201105-CA0I-R51S-5DRT-TCZRPR5P0NLB-low.gifFigure 5-1 BQA Package, 14-Pin WQFN (Top View)
GUID-7B2146FD-DB98-4805-AE9A-4367DEE7C744-low.gifFigure 5-2 PW Package, 14-Pin TSSOP (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
1CLR 1 Input Clear for channel 1, active low
1D 2 Input Data for channel 1
1CLK 3 Input Clock for channel 1, rising edge triggered
1PRE 4 Input Preset for channel 1, active low
1Q 5 Output Output for channel 1
1Q 6 Output Inverted output for channel 1
GND 7 — Ground
2Q 8 Output Inverted output for channel 2
2Q 9 Output Output for channel 2
2PRE 10 Input Preset for channel 2, active low
2CLK 11 Input Clock for channel 2, rising edge triggered
2D 12 Input Data for channel 2
2CLR 13 Input Clear for channel 2, active low
VCC 14 — Positive supply
Thermal Pad(1) — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply
(1) BQA package only.