SN74LV2T74 Dual D-Type Flip-Flop With Integrated Translation

1 Features

Wide operating range of 1.8 V to 5.5 V
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
  - 1.2 V to 1.8 V
  - 1.5 V to 2.5 V
  - 1.8 V to 3.3 V
  - 3.3 V to 5.0 V
- Down translation:
  - 5.0 V, 3.3 V, 2.5 V to 1.8 V
  - 5.0 V, 3.3 V to 2.5 V
  - 5.0 V to 3.3 V
5.5-V tolerant input pins
Supports standard pinouts
Up to 150 Mbps with 5-V or 3.3-V V_CC
Latch-up performance exceeds 250 mA
per JESD 17

2 Applications

Convert a momentary switch to a toggle switch
Hold a signal during controller reset
Input slow edge-rate signals
Operate in noisy environments
Divide a clock signal by two

3 Description

The SN74LV2T74 contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V_CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

Package Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽²⁾	BODY SIZE (NOM)⁽³⁾
SN74LV2T74	BQA (WQFN, 14)	3 mm × 2.5 mm	3 mm × 2.5 mm
SN74LV2T74	PW (TSSOP, 14)	5 mm × 6.4 mm	5 mm × 4.4 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

(3) The body size (length × width) is a nominal value and does not include pins.

Simplified Logic Diagram (Positive Logic)

4 Revision History

DATE	REVISION	NOTES
May 2023	*	Initial Release

5 Pin Configuration and Functions

Figure 5-1 BQA Package, 14-Pin WQFN (Top View)

Figure 5-2 PW Package, 14-Pin TSSOP (Top View)

Table 5-1 Pin Functions

PIN		TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
1CLR	1	Input	Clear for channel 1, active low
1D	2	Input	Data for channel 1
1CLK	3	Input	Clock for channel 1, rising edge triggered
1PRE	4	Input	Preset for channel 1, active low
1Q	5	Output	Output for channel 1
1Q	6	Output	Inverted output for channel 1
GND	7	—	Ground
2Q	8	Output	Inverted output for channel 2
2Q	9	Output	Output for channel 2
2PRE	10	Input	Preset for channel 2, active low
2CLK	11	Input	Clock for channel 2, rising edge triggered
2D	12	Input	Data for channel 2
2CLR	13	Input	Clear for channel 2, active low
V_CC	14	—	Positive supply
Thermal Pad⁽¹⁾		—	The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply

(1) BQA package only.