SCLS979 November   2023 SN74LV3T98-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Noise Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Clamp Diode Structure
      3. 7.3.3 SCxT Enhanced Input Voltage
        1. 7.3.3.1 Down Translation
        2. 7.3.3.2 Up Translation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Logic Configurations
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Wide operating range of 1.8 V to 5.5 V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V VCC
  • Latch-up performance exceeds 250 mA per JESD 17
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability