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  • SN74LV4040A 12-Bit Asynchronous Binary Counters

    • SCES226K April   1999  – September 2024 SN74LV4040A

      PRODMIX  

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  • SN74LV4040A 12-Bit Asynchronous Binary Counters
  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics
    6. 4.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
    7. 4.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 4.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 4.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    10. 4.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 4.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 4.12 Noise Characteristics
    13. 4.13 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
  12. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • PW|16
  • NS|16
  • N|16
  • RGY|16
  • D|16
  • DGV|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
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SN74LV4040A 12-Bit Asynchronous Binary Counters

1 Features

  • 2V to 5.5V VCC operation
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) 2.3V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode voltage operation on all ports
  • High on-off output-voltage ratio
  • Low crosstalk between switches
  • Individual switch controls
  • Extremely low input current
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, class II

2 Description

The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74LV4040A N (PDIP, 16) 19.3mm x 9.4mm 19.3mm x 6.35mm
D (SOIC, 16) 9.9mm x 6mm 9.9mm x 3.9mm
NS (SOP, 16) 10.2mm x 7.8mm 10.2mm x 5.3mm
DB (SSOP, 16) 6.2mm x 7.8mm 6.2mm x 5.3mm
PW (TSSOP, 16) 5mm x 6.4mm 5mm x 4.4mm
DGV (TVSOP, 16) 3.6mm x 6.4mm 3.6mm x 4.4mm
RGY (VQFN, 16) 4mm x 3.5mm 4mm x 3.5mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN74LV4040A Logic Diagram (Positive Logic)Logic Diagram (Positive Logic)

3 Pin Configuration and Functions

SN74LV4040A SN74LV4040A D, DB, DGV, N, NS, or PW Package (Top View)Figure 3-1 SN74LV4040A D, DB, DGV, N, NS, or PW Package (Top View)
SN74LV4040A SN74LV4040A RGY Package (Top View)
A. NC - no internal connection
Figure 3-2 SN74LV4040A RGY Package (Top View)
PIN TYPE(1) DESCRIPTION
NAME NO.
QL 1 O QL output
QF 2 O QF output
QE 3 O QE output
QG 4 O QG output
QD 5 O QD output
QC 6 O QC output
QB 7 O QB output
GND 8 - Ground
QA 9 O QA output
CLK 10 I Clock, falling edge triggered
CLR 11 I Clear, active high
QI 12 O QI output
QH 13 O QH output
QJ 14 O QJ output
QK 15 O QK output
VCC 16 - Positive supply
(1) I = input, O = output

 
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