SCES656E
February 2006 – November 2016
SN74LV4046A
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DGV|16
MPDS006C
N|16
MPDI002C
PW|16
MPDS361A
D|16
MPDS178G
NS|16
MPDS551A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sces656e_oa
sces656e_pm
5
Pin Configuration and Functions
D, DGV, NS, N, or PW Package
16-Pin SOIC, TVSOP, SO, PDIP, or TSSOP
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
PCP
OUT
O
Phase comparator pulse output
2
PC1
OUT
O
Phase comparator 1 output
3
COMP
IN
I
Comparator input
4
VCO
OUT
O
VCO output
5
INH
I
Inhibit input
6
C1
A
—
Capacitor C1 connection A
7
C1
B
—
Capacitor C1 connection B
8
GND
—
Ground (0 V)
9
VCO
IN
I
VCO input
10
DEM
OUT
O
Demodulator output
11
R
1
—
Resistor R1 connection
12
R
2
—
Resistor R2 connection
13
PC2
OUT
O
Phase comparator 2 output
14
SIG
IN
I
Signal input
15
PC3
OUT
O
Phase comparator 3 output
16
V
CC
—
Positive supply voltage