SCLS520F August   2003  – June 2024 SN74LV4051A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information: SN74LV4051A-Q1
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics VCC = 2.5V ± 0.2V
    7. 5.7 Timing Characteristics VCC = 3.3V ± 0.3V
    8. 5.8 Timing Characteristics VCC = 5V ± 0.5V
    9. 5.9 AC Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • DW|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

SN74LV4051A-Q1 D or PW Package, 16-Pin SOIC or TSSOP (Top View) Figure 4-1 D or PW Package, 16-Pin SOIC or TSSOP (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
Y4 1 I(2) Input to mux
Y6 2 I(2) Input to mux
COM 3 O(2) Output of mux
Y7 4 I(2) Input to mux
Y5 5 I(2) Input to mux
INH 6 I(2) Enables the outputs of the device. Logic low level with turn the outputs on, high level will turn them off.
GND 7 — Ground
GND 8 — Ground
C 9 I Selector line for outputs (see Section 7.4 for specific information)
B 10 I Selector line for outputs (see Section 7.4 for specific information)
A 11 I Selector line for outputs (see Section 7.4 for specific information)
Y3 12 I(2) Input to mux
Y0 13 I(2) Input to mux
Y1 14 I(2) Input to mux
Y2 15 I(2) Input to mux
Vcc 16 I Device power input
(1) I = input, O = output
(2) These I/O descriptions represent the device when used as a multiplexer, when this device is operated as a demultiplexer pins Y0-Y7 may be considered outputs (O) and the COM pin may be considered inputs (I).