SCLS428K May   1999  – September 2024 SN74LV4051A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information: SN74LV4051A
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Characteristics VCC = 2.5 V ± 0.2 V
    7. 5.7  Timing Characteristics VCC = 3.3 V ± 0.3 V
    8. 5.8  Timing Characteristics VCC = 5 V ± 0.5 V
    9. 5.9  AC Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • PW|16
  • DYY|16
  • NS|16
  • N|16
  • RGY|16
  • D|16
  • DGV|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

SN74LV4051A D, PW, or DYY Packages, 16-Pin SOIC, TSSOP, or SOT-23-THIN (Top View)Figure 4-1 D, PW, or DYY Packages, 16-Pin SOIC, TSSOP, or SOT-23-THIN (Top View)
SN74LV4051A RGY Package 16-Pin VQFN With Exposed Thermal Pad (Top View)Figure 4-2 RGY Package 16-Pin VQFN With Exposed Thermal Pad (Top View)
Table 4-1 Pin Functions
PIN TYPE(2) DESCRIPTION
NAME NO.
A 11 I Selector line A for outputs (see Section 7.4 for specific information)
B 10 I Selector line B for outputs (see Section 7.4 for specific information)
C 9 I Selector line C for outputs (see Section 7.4 for specific information)
COM 3 O/I(1) Output/Input of mux
GND 7, 8 — Ground
INH 6 I(1) Enables the outputs of the device. Logic low level with turn the outputs on, high level will turn them off.
Y0 13 I/O(1) Input/Output to mux
Y1 14 I/O(1) Input/Output to mux
Y2 15 I/O(1) Input/Output to mux
Y3 12 I/O(1) Input/Output to mux
Y4 1 I/O(1) Input/Output of mux
Y5 5 I/O(1) Input/Output to mux
Y6 2 I/O(1) Input/Output to mux
Y7 4 I/O(1) Input/Output to mux
VCC 16 — Device power
(1) These I/O descriptions represent the device when used as a multiplexer, when this device is operated as a demultiplexer pins Y0-Y7 may be considered outputs (O) and the COM pin may be considered inputs (I).
(2) I = inputs, O = outputs