SCLS412K April   1998  – February 2023 SN74LV574A

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
    7. 6.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 6.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 6.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    10. 6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 6.12 Noise Characteristics
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Latching Logic
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGV|20
  • DB|20
  • NS|20
  • DW|20
  • PW|20
  • RGY|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20221118-SS0I-HHQR-TRXG-VNWF91RQNM5S-low.pngFigure 5-1 DB, DGV, DW, NS, or PW Package (Top View)
GUID-20221118-SS0I-DGBZ-WNP0-8JNWRSRHV7HR-low.pngFigure 5-2 RGY Package (Top View)
Table 5-1 Pin Functions
PIN TYPE Description
NO. NAME
1 OE I Clear all channels, active low
2 1D I Channel 1, D input
3 2D I Channel 2, D input
4 3D I Channel 3, D input
5 4D I Channel 4, D input
6 5D I Channel 5, D input
7 6D I Channel 6, D input
8 7D I Channel 7, D input
9 8D I Channel 8, D input
10 GND — Ground
11 CLK I Clock Pin
12 8Q O Channel 8, Q output
13 7Q O Channel 7, Q output
14 6Q O Channel 6, Q output
15 5Q O Channel 5, Q output
16 4Q O Channel 4, Q output
17 3Q O Channel 3, Q output
18 2Q O Channel 2, Q output
19 1Q O Channel 1, Q output
20 VCC — Power Pin