SCLS887 December   2022 SN74LV594A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: VCC = 2.5 V ± 0.2 V
    7. 6.7  Switching Characteristics: VCC = 3.3 V ± 0.3 V
    8. 6.8  Switching Characteristics: VCC = 5 V ± 0.5 V
    9. 6.9  Timing Requirements: VCC = 2.5 V ± 0.2 V
    10. 6.10 Timing Requirements: VCC = 3.3 V ± 0.3 V
    11. 6.11 Timing Requirements: VCC = 5 V ± 0.5 V
    12. 6.12 Noise Characteristics
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Timing Requirements: VCC = 2.5 V ± 0.2 V

over recommended operating free-air temperature range. See Figure 6-1.
TA = 25°C –40°C TO 125°C UNIT
MIN MAX MIN MAX
tw Pulse duration RCLK or SRCLK high or low 7 8.5 ns
RCKR or SCRCLR low 6 7.5
tsu Setup time SER before SRCLK↑ 5.5 6 ns
SRCLK↑ before RCLK↑ 8 10
SCRCLR low before RCLK↑(1) 8.5 10.5
SRCLR high (inactive) before SRCLK↑ 6 7.5
RCLK high (inactive) before RCLK↑ 6.7 8.5
th Hold time SER after SRCLK↑ 1.5 2 ns
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.