SCLS539G August   2003  – March 2023 SN74LV595A-Q1

PRODMIX  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
    7. 6.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 6.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 6.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    10. 6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 6.12 Timing Diagrams
    13. 6.13 Noise Characteristics
    14. 6.14 Operating Characteristics
    15. 6.15 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Latching Logic
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 Wettable Flanks
      5. 8.3.5 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Power Considerations
      2. 9.2.2 Input Considerations
      3. 9.2.3 Output Considerations
      4. 9.2.4 Detailed Design Procedure
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Recommended Operating Conditions

MINMAXUNIT
VCCSupply voltage25.5V
VIHHigh-level input voltageVCC = 2 V1.5V
VCC = 2.3 V to 2.7 VVCC × 0.7
VCC = 3 V to 3.6 VVCC × 0.7
VCC = 4.5 V to 5.5 VVCC × 0.7
VILLow-level input voltageVCC = 2 V0.5V
VCC = 2.3 V to 2.7 VVCC × 0.3
VCC = 3 V to 3.6 VVCC × 0.3
VCC = 4.5 V to 5.5 VVCC × 0.3
VIInput voltage(1)05.5V
VOOutput voltageHigh or low state0VCCV
3-state05.5
IOHHigh level output currentVCC = 2 V–50µA
VCC = 2.3 V to 2.7 V–2mA
VCC = 3 V to 3.6 V–8
VCC = 4.5 V to 5.5 V–16
IOLLow level output currentVCC = 2 V50µA
VCC = 2.3 V to 2.7 V2mA
VCC = 3 V to 3.6 V8
VCC = 4.5 V to 5.5 V16
Δt/ΔvInput transition rise/fall timeVCC = 2.3 V to 2.7 V200ns/V
VCC = 3 V to 3.6 V100
VCC = 4.5 V to 5.5 V20
TAOperating free-air temperatureSN74LV595AIPWRQ1–4085°C
SN74LV595AQPWRQ1

or SN74LV595AQWBQRQ1

–40125
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs.