SCLS937 august   2023 SN74LV6T06

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Noise Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Open-Drain CMOS Outputs
      2. 8.3.2 LVxT Enhanced Input Voltage
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.

The outputs are measured individually with one input transition per measurement.

TEST S1 RL CL ΔV VCC
tPLZ, tPZL CLOSED 1 kΩ 15 pF, 50 pF 0.15 V ≤ 2.5 V
tPLZ, tPZL CLOSED 1 kΩ 15 pF, 50 pF 0.3 V > 2.5 V

GUID-FC79FB8A-412C-432D-BA5D-30192BE732A9-low.gif
(1) CL includes probe and test-fixture capacitance.
Figure 7-1 Load Circuit for Open-Drain Outputs
GUID-20230721-SS0I-VJQB-BMGP-K0S1JW76FHMX-low.svg
Noise values measured with all other outputs simultaneously switching.
Figure 7-3 Voltage Waveforms, Noise
GUID-AE3EF74C-6BDA-47C2-BBB1-D89A3DFACB9B-low.gif
(1) tPLZ is the same as tdis.
(2) tPZL is the same as ten.
Figure 7-2 Voltage Waveforms Propagation Delays