SCLS981 January   2024 SN74LV6T17-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Noise Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Clamp Diode Structure
      3. 7.3.3 CMOS Schmitt-Trigger Inputs
      4. 7.3.4 LVxT Enhanced Input Voltage
        1. 7.3.4.1 Down Translation
        2. 7.3.4.2 Up Translation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4.1 Down Translation

Signals can be translated down using the SN74LV6T17-EP. The voltage applied at the VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables.

When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0V in the LOW state. As shown in Figure 7-2, ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5V, and input signals in the LOW state are lower than VIL(MAX).

As shown in Figure 7-3 for example, the standard CMOS inputs for devices operating at 5.0V, 3.3V or 2.5V can be down-translated to match 1.8V CMOS signals when operating from 1.8V VCC.

Down Translation Combinations are as follows:

  • 1.8V VCC – Inputs from 2.5V, 3.3V, and 5.0V
  • 2.5V VCC – Inputs from 3.3V and 5.0V
  • 3.3V VCC – Inputs from 5.0V