SCLS556C december   2003  – august 2023 SN74LV74A-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Revision History
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, VCC = 2.5 V ±0.2 V
    7. 5.7  Timing Requirements, VCC = 3.3 V ±0.3 V
    8. 5.8  Timing Requirements, VCC = 5 V ±0.5 V
    9. 5.9  Switching Characteristics, VCC = 2.5 V ±0.2 V
    10. 5.10 Switching Characteristics, VCC = 3.3 V ±0.3 V
    11. 5.11 Switching Characteristics, VCC = 5 V ±0.5 V
    12. 5.12 Noise Characteristics
    13. 5.13 Operating Characteristics
  7. 6Parameter Measurement Information
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V VCC operation.

Package Information
PART NUMBER PACKAGE1 PACKAGE SIZE2
SN74LV74A-Q1 PW (TSSOP, 14) 5.00 mm × 6.4 mm
D (SOIC, 14) 8.65 mm x 6 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-8DBEF82E-F380-4062-8CC0-605EA0242177-low.gif Logic Diagram, Each Flip-flop (Positive Logic)