SCLS381M August   1997  – March 2015 SN74LV74A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Electrical Characteristics
    5. 6.5  Switching Characteristics: VCC = 2.5 V ± 0.2 V
    6. 6.6  Switching Characteristics: VCC = 3.3 V ± 0.3 V
    7. 6.7  Switching Characteristics: VCC = 5 V ± 0.5 V
    8. 6.8  Timing Requirements: VCC = 2.5 V ± 0.2 V
    9. 6.9  Timing Requirements: VCC = 3.3 V ± 0.3 V
    10. 6.10 Timing Requirements: VCC = 5 V ± 0.5 V
    11. 6.11 Noise Characteristics
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 8.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down
    Mode Operation
  • Latch-up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 500-V Charged-Device Model (C101)

2 Applications

  • Programmable Logic Controller (PLC)
  • DCS and PAC: Analog Input Module
  • AV Receiver
  • Server PSU
  • STB, DVR, and Streaming Media (Withdraw)
  • Server Motherboard

3 Description

These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LV74A VQFN (14) 3.50 mm × 3.50 mm
SOIC (14) 8.65 mm × 3.91 mm
SOP (14) 10.30 mm × 5.30 mm
SSOP (14) 6.20 mm × 5.30 mm
TSSOP (14) 5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram, Each Flip-Flop
(Positive Logic)

SN54LV74A SN74LV74A logic_cls381.gif