SCLS589B August   2004  – May 2020 SN74LV8154

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. Table 1. Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics - VCC = 3.3 V ± 0.3 V
    8. 6.8  Switching Characteristics VCC = 5 V ± 0.5 V
    9. 6.9  Noise Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Overview

The SN74LV8154 device is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation. The counters have dedicated clock inputs. The counters share a storage register clock and an asynchronous clear input. The 32-bit storage register can be mapped on the output bus 8-bit at a time. Four bus reads are needed to access the contents of both counters. The two counters can be chained by connecting CLKBEN to RCOA

This 16-bit counter (A or B) feeds a 16-bit storage register, and each storage register is further divided into an upper byte and lower byte. The GAL, GAU, GBL, GBU inputs are used to select the byte that needs to be output at Y0−Y7. CLKA is the clock for A counter, and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered.

A 32-bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.

To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.