SCLS589B August   2004  – May 2020 SN74LV8154

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. Table 1. Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics - VCC = 3.3 V ± 0.3 V
    8. 6.8  Switching Characteristics VCC = 5 V ± 0.5 V
    9. 6.9  Noise Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

N or PW Package
20-Pin PDIP or TSSOP
Top View
SN74LV8154 po_cls589.gif

Table 1. Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CCLR 11 I Clock clear, asyncrounous active-low clear for both counters
CLKA 1 I Clock A, rising edge count clock
CLKB 2 I Clock B, rising edge count clock
CLKBEN 9 I Clock B enable, active-low allows clocking for counter B; connect to RCOA for 32-bit counter.
GAL 3 I Gate A lower byte, active-low puts lower byte of stored counter A on the Y bus.
GAU 4 I Gate A upper byte, active-low puts upper byte of stored counter A on the Y bus.
GBL 5 I Gate B lower byte, active-low puts lower byte of stored counter B on the Y bus.
GBU 6 I Gate B upper byte, active-low puts upper byte of stored counter B on the Y bus.
GND 10 — Ground
RCLK 7 I Register Clock, rising edge stores counters into an internal storage register.
RCOA 8 O Ready case overflow A, active low when counter A is full count and ready to overflow on next clock A.
VCC 20 — Power supply pin
Y0 19 O Data output bit 0 (LSB)
Y1 18 O Data output bit 1
Y2 17 O Data output bit 2
Y3 16 O Data output bit 3
Y4 15 O Data output bit 4
Y5 14 O Data output bit 5
Y6 13 O Data output bit 6
Y7 12 O Data output bit 7 (MSB)