SCLS951A August   2023  – November 2023 SN74LV8T165-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LVxT Enhanced Input Voltage
        1. 7.3.1.1 Down Translation
        2. 7.3.1.2 Up Translation
      2. 7.3.2 Balanced CMOS Push-Pull Outputs
      3. 7.3.3 Latching Logic with Known Power-Up State
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Application Information

The SN74LV8T165-Q1 is a parallel-input shift register, which can be used to reduce the number of required inputs on a system controller very significantly in some applications. Parallel data is loaded into the shift register, then the stored data can be loaded into a serial input of the system controller by clocking the shift register.

Multiple shift registers can be cascaded to provide more data inputs while still only using a single serial input to the system controller. This process is primarily limited by the required data input rate and timing characteristics of the selected shift register, as defined in the Timing Characteristics and Switching Characteristics tables.

An example block diagram is shown for using a single shift register in the following Typical Application Block Diagram.